The present invention relates to a cache circuit for controlling cache memory.
In general, in a computer system, cache memory, which is smaller in memory capacity but faster in processing speed than main memory, is provided between a central processing unit (CPU) and the main memory slow in processing speed compared with the CPU.
The cache memory temporarily holds a copy of an instruction code or data in the main memory to increase the apparent processing speed of the main memory as is observed from the CPU (see Akihiro Hashimoto “Joho Kogaku Nyumon Sensho (Selection of Introductions to Information Engineering) 7, Computer Architecture”, Shokodo, Jul. 20, 1995).
A bus is provided between the CPU and the main memory for transfer of instruction codes and data stored in the main memory. In a computer system, the operation of the bus is examined and evaluated in some cases. In such examination and evaluation of the operation of the bus, a program is executed to allow the CPU to perform instruction accessing and data accessing to the main memory repeatedly under various conditions. Such a program generally has a loop structure in many cases to allow for the CPU's repeated access to the main memory.
In the case that a loop-structured program is executed in a computer system having cache memory, if all of instruction codes in the loop are held in cache memory for instruction codes (instruction cache memory), no instruction access to the main memory will be made, and it will be only data based on data access by the CPU that is transferred through the bus.
Also, if all of data in the loop for which access is made to the main memory are held in cache memory for data (data cache memory), no data access to the main memory will be made, and it will be only instruction codes based on instruction access by the CPU that are transferred through the bus.
In the above situation, examination of the operation of the bus in the state that instruction access and data access to the main memory are steadily made will not be attained.
To solve the above problem, a conventional computer system sets a timer provided therein to allow a timer interrupt against the CPU to occur every fixed time. If the CPU detects a timer interrupt, entries in the instruction cache memory or the data cache memory are disabled with a program, to cause access to the main memory via the bus for an instruction code or data stored therein.
However, the method of disabling the cache using a timer interrupt with a program has the following problem. Since the access speed is different among the types of main memory such as static random access memory (SRAM), synchronous dynamic random access memory (SDRAM) and flash read-only memory (flash ROM), the period of the timer interrupt must be set optimally for each type of main memory.
As another problem, the increase rate of the cache hit rate is not constant depending on the operation of a program. Therefore, with the periodical disabling of the cache memory using timer interrupts, the cache hit rate may increase and thus the state of having no access to the main memory may possibly continue long.
An object of the present invention is providing a cache circuit capable of avoiding decrease in access to main memory due to increase in cache hit rate to ensure execution of examination of the operation of a bus in the state that instruction access and data access to the main memory are steadily made.